1. Field of the Invention
The present invention relates to a comparable circuit for testing DRAM devices, and more particularly, to a comparable circuit for parallel testing the DRAM devices with self-diagnostic mechanism.
2. Description of the Prior Art
The approaches of the memory devices bring the modern electrical devices broadly employed in human"" lives because the kernels of the electrical devices, which are usually the microprocessors and microcomputers, store or retrieve their currently used data from memories on-chip therein. Those commonly used memory devices, especially DRAM (dynamic random access memory) devices, are broadly used memories due to their cost and operation speeds. In the present days, a high density DRAM device having 220 bits or more has been developed in an integrated circuit. A testing procedure is thus unavoidable especially when the DRAM devices are mass-produced.
Nowadays, parallel testing becomes a common used approach for testing whether a DRAM device is fault because many DRAM devices can be detected simultaneously. Please refer to FIG. 1, which depicts a 4Mxc3x974 DRAM device 100 composed of four 1Mxc3x974 memory cells 100A, 100B, 100C, and 100D to be parallel detected in U.S. Pat. No. 4,860,259 disclosed by Tobita. I/O bus having four testing signals IO0, IO1, IO2, IO3, are routed into the detected cells 100A to 100D simultaneously but accompanied with a control signal Stest for indicating the testing period. For example, Stest can be pulled to high (logic 1) under a WCBR (Write CAS (Column Address Strobe) Before RAS (Row Address Strobe)) specification and accompanied with a test pattern loaded on IO0, IO1, IO2, and IO3. Four I/O blocks (IOBLK) 102A, 102B, 102C, and 102D latch the loaded test pattern and direct it to cells 100A, 100B, 100C, and 100D for storing when selection signals SECA, SECB, SECC, and SECD are enabled, respectively. Next, the stored test pattern is read from cells 100A, 100B, 100C, and 100D and then routed to a associated comparable circuit for detecting whether the test pattern is written correctly. Each one of the comparable circuits 104A, 104B, 104C, and 104D consists of two exclusive OR (XOR) gates 106 and 108, an OR gate 110 and a tri-state output buffer 112 to generate a one bit output by using the test pattern. The one bit output is then respectively routed on IO0, IO1, IO2, and IO3 according to their sections. Accordingly, by detecting the logic states from IO0, IO1, IO2, and IO3 can decide whether the detected memory cell is defective or not. For example, if a test pattern {0000} that is stored in then read out from the memory cell 100A, both outputs of the XOR gates are logic 0 because all their input terminals receive logic 0 as inputs. Obviously, the outputs of both the OR gate 110 and output buffer 112 are logic 0, which indicates the detected memory cell is perfect. In contrast, if logic 1 appears on the output buffer, the detected memory cell can be concluded as defective because an error evidently occurs when retrieving the stored test pattern. As noted, logic 1 and logic 0 appear on I/O bus indicate an error or a normal condition is obtained in the testing procedure according to WCBR specification. One disadvantage of the Tobita reference is that only four test patterns {0000}, {0011}, {1100} and {1111} can be used in the comparable circuit. Any test pattern having different logic states at two input terminals of the XOR gates 106 or 108 will cause the output buffer 112 to output logic 1, the detected memory cell is thus treated as defective even it is perfect. Additional test procedures are thus unavoidable for testing DRAM devices.
Another conventional approach, such as the circuits disclosed by McClure et al in U.S. Pat. No. 5,265,100 is also shown in FIG. 2 for testing the DRAM devices. In McClure reference, four comparable circuits 204A, 204B, 204C and 204D are provided for detecting the retrieved test patterns from the memory cells 100A, 100B, 100C and 100D, respectively. Each one of the comparable circuits 204A, 204B, 204C and 204D is composed of two exclusive NOR (XNOR) gates 206 and 208, a NADN gate 210, and a tri-state output buffer 212. Operations of the McClure reference are similar to Tobita reference except the comparable circuits are. For example, a testing pattern is also loaded on IO0, IO1, IO2, and IO3, and directed into the detected devices 100A to 100D simultaneously, a control signal Stest is also accompanied with to indicate the testing period. Four one bit outputs of the output buffers 212 are also respectively routed on IO0, IO1, IO2, and IO3 according to their sections. However, only four test patterns as the Tobita reference""s can be used in McClure reference because any test pattern having different logic states at two input terminals of the XNOR gates 206 or 208 will cause the output buffer 212 to be logic 1. Additional test procedures are also unavoidable because the detected memory cell will also be treated as defective even it is perfect. On the other hand, another fatal disadvantage of the above two references is that it is impossible to distinguish whether a detected memory cell is defective when the comparable circuit is imperfect. Please refer to FIG. 4A, which depicts a short circuit 214 occurs between two input terminals (nodes E and F) of the NAND gate 210. Obviously, nodes E and F always keep the same logic state due to the short circuit 214 whatever the logic states of nodes A, B, C, and D are. Therefore, the logic state of node G (also the input terminal of the output buffer 212) can not correctly indicate the currently detecting situation. A need has arisen to disclose a comparable circuit, in which the disadvantages of the conventional schemes, such as fewer test patterns can be employed and it is impossible to distinguish whether the comparable circuit or the detected memory cell is defective, can be completely overcome.
The principal object of the invention is to provide a comparable circuit for parallel detecting DRAM devices with more test patterns.
The other object of the invention is to provide a comparable circuit with self-diagnostic mechanism.
According to the aforementioned objects, the disclosed comparable circuit basically includes a three-stage circuit composed of two XNOR gates, a XOR gate, and a tri-state output buffer. The first stage consisting of the XOR gate and a first XNOR gate parallel receive the stored test pattern from the detected memory cell to respectively generate the first comparison results. A second exclusive XNOR gate included in the second stage receives the comparison results from the first stage as inputs, and connects with the third stage through an output terminal of the second XNOR gate. The third stage composed of the output buffer couples with the output terminal of the second XNOR gate to generate the second comparison result routed on I/O bus. Chess-like test patterns can be employed in the disclosed comparable circuit due to two mutually exclusive logic gates are applied in the first stage. On the other hand, logic 1 freezes on I/O bus if two input terminals of the second XNOR gate are shorted, which indicates the comparable circuit is defective.